1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device comprising first conductive type source/drains region and second conductive type source/drain regions.
2. Description of the Background Art
A dual-gate CMOS (complementary metal oxide semiconductor) device constituted of an n-channel MOS transistor having n-type source/drain regions and a gate electrode formed by an n-type polysilicon layer and a p-channel MOS transistor having p-type source/drain regions and a gate electrode formed by a p-type polysilicon layer is known in general. In this conventional dual-gate CMOS device, the gate electrodes of the n- and p-channel MOS transistors formed by the polysilicon layers are disadvantageously depleted. In this regard, there is proposed a dual-gate CMOS device capable of solving this problem of depletion of gate electrodes (refer to Japanese Patent Laying-Open No. 2004-165346, for example).
In the dual-gate CMOS device proposed in the aforementioned Japanese Patent Laying-Open No. 2004-165346, gate electrodes of n- and p-channel MOS transistors are formed by metal layers, for solving the problem of depletion of gate electrodes of a semiconductor (polysilicon).
In the dual-gate CMOS device proposed in the aforementioned Japanese Patent Laying-Open No. 2004-165346, however, the gate electrodes of the n- and p-channel MOS transistors are constituted of only the metal layers formed to cover the overall upper surfaces of corresponding gate insulating films respectively, to disadvantageously increase the difference between the thermal expansion coefficients of the gate electrodes and a substrate formed with the gate insulating films and source/drain regions. After heat treatment at a temperature of about 1000° C., therefore, stress acting between the gate electrodes and the gate insulating films and the substrate is so increased that electron mobility in the substrate is deteriorated due to this stress.